[PATCH] Configure: Fix cacheline size for aarch64 platforms
mdounin at mdounin.ru
Fri Dec 8 19:48:05 UTC 2017
On Fri, Dec 08, 2017 at 06:43:15PM +0000, debayang.qdt wrote:
> 64 bytes should be the minimum size.
Any links to support this claim?
> However, A53 is a small segment of arm64 based servers .
> Multiple aarch64 based servers uses 128 byte cache lines.
> For e.g Centriq 2400 aarch64 server from Qualcomm Datacenter Technologies uses 128 bytes cache line.
AFAIK, using a smaller cache line size is mostly fine and imply
almost no performance difference in nginx. On ther other hand,
using larger cache line size can easily result in multiple memory
access where just one should be enough, resulting in suboptimal
performance. That's why we generally assume 32 unless we know
> To be very accurate , we may read the dcache line size from CTR_EL0 register.
> Let me know what you think.
Given the level of popularity of aarch64 servers, I would rather
not. I would prefer to rely on something architecture-independent
like sysconf(_SC_LEVEL1_DCACHE_LINESIZE), though it looks like it
doesn't work on aarch64 yet, see
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